The present invention relates in general to integrated circuits and in particular to programmable differential output circuits.
To meet the demands of today's applications, integrated circuits are being designed to operate at higher speeds with lower power supply voltages. One technique for enabling high frequency operation at lower voltages is differential signaling. In differential signaling, logic levels are represented by the difference between a pair of complementary signals. Instead of processing signals that swing between the power supplies, circuits designed to process differential signals need only detect a relatively small difference in voltage between the two complementary signals. The much smaller voltage swing and the lower voltage level characteristics of differential signaling facilitate high speed operation at lower voltages.
Integrated circuits that transmit differential signals externally require a differential output buffer or output driver circuit. The design of a differential output driver is dictated by a set of specifications that defines the speed and output voltage level requirements for a given loading condition. To support these often stringent specifications the output transistors of a typical differential driver circuit are required to source or sink large amounts of current at high switching speeds. Differential output drivers are therefore commonly designed with very large output transistors. Larger output transistors, however, exhibit undesirable parasitic effects and result in increased silicon area and therefore costs. Further, because over the years different standards have evolved for differential signaling, an output driver that is designed to meet one set of specifications may not be suitable for applications using a different standard. An output driver that is designed to support multiple standards is often designed for the worst case specification, which typically results in inefficient circuits that employ larger device sizes and consume larger DC operating currents. There is therefore a need for a differential output driver circuit that consumes less silicon area and lower DC current, and that can support multiple specifications defined by various differential signaling standards without sacrificing area and power consumption.